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INTEGRATED CIRCUITS
DATA SHEET
SAA3500H Digital audio broadcast channel decoder
Preliminary specification File under Integrated Circuits, IC01 2000 Jun 14
Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
CONTENTS 1 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.7.1 9.7.2 9.7.3 10 FEATURES APPLICATIONS GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION INTERFACE DESCRIPTION Input interface Memory interface Parallel output interface Serial output interface Simple full capacity output RDI output Microcontroller interface I2C-bus mode L3-bus mode Microcontroller interface registers LIMITING VALUES 16.2 16.3 16.4 16.5 17 18 19 20 11 12 13 14 14.1 14.2 14.3 15 16 16.1
SAA3500H
THERMAL CHARACTERISTICS DC CHARACTERISTICS AC CHARACTERISTICS APPLICATION INFORMATION Clock oscillator Reset input Boundary scan test interface PACKAGE OUTLINE SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS PURCHASE OF PHILIPS I2C COMPONENTS
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Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
1 FEATURES
SAA3500H
* Digital Audio Broadcast (DAB) full-capacity demodulator and decoder * Supports DAB transmission modes I, II, III and IV * Integrated Analog-to-Digital Converter (ADC) for IF input * Digital mixer with on-chip digital Automatic Frequency Control (AFC) and Automatic Gain Control (AGC) * Detectors for null symbol, DAB mode and transmitter identification * On-chip or external synchronization algorithms and control loops * On-chip timing PLL and DCXO * Dynamic DAB multiplex reconfiguration supported * Equal and unequal error protection for up to 64 sub-channels * Fast information channel buffering * Simple full capacity output * Receiver data interface * Serial output for three sub-channels * I2C-bus or L3-bus control interface. 2 APPLICATIONS * Mobile receivers (FM/DAB car radios) * Personal Computer add-ons * Test and measurement equipment * Portable radios. 3 GENERAL DESCRIPTION
The Philips SAA3500H is a Digital Audio Broadcast (DAB) channel decoder according to the ETSI specification ETS 300 401. The SAA3500H is a successor to the Philips FADIC and SIVIC chip set and provides an IF ADC, digital mixer, full DAB ensemble demodulation and decoding as well as time and frequency synchronization functions. Because of the full-speed Viterbi decoding capacity and a high-speed receiver data output interface, DAB data reception is not limited by the SAA3500H channel decoder.
4
QUICK REFERENCE DATA SYMBOL PARAMETER supply voltage maximum input voltage DC supply current clock frequency ambient temperature storage temperature MIN. 3.0 -0.5 - - -40 -65 3.3 - - 24576 +25 - TYP. 3.6 VDD + 0.5 180 - +85 +150 MAX. V V mA kHz C C UNIT
VDD Vi(max) IDD fclk Tamb Tstg 5
ORDERING INFORMATION PACKAGE TYPE NUMBER NAME DESCRIPTION plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.7 mm; high stand-off height VERSION SOT317-1
SAA3500H
QFP100
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Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
6 BLOCK DIAGRAM
SAA3500H
BYP AIF 2 INP[9:0] 17 to 8
AGC SLI
ADCLK
OSCI OSCO 4 5
IQS
MCLK 19 41
21 20 25 24
ADE ADC
99 1
AD CONVERTER (8 BIT)
DIGITAL MIXER AND FILTERS
NULL DETECTOR, TIMEBASE, DCXO
23 22
FSO FSI
OUT[7:0] OCLK OIQ OCIR OEN
39 to 32 27 CHANNEL IMPULSE 29 RESPONSE PROCESSOR 30 31 sync
FAST FOURIER TRANSFORMATION
BOUNDARY SCAN TEST
97 95 96 93 98
TMS TCK TDI TDO TRST
AUTOMATIC FREQUENCY CONTROL PROCESSOR
DIFFERENTIAL DEMODULATOR metrics
SAA3500H
70 62 to 68, 81 to 91 71 to 78 69 61 A17 A[17:0] D[7:0] RD WR
SYMBOL SELECT CAPACITY UNIT SELECT
FREQUENCY & TIME DE-INTERLEAVER
UNEQUAL/EQUAL ERROR PROTECTION CONTROL MCI MICROCONTROLLER INTERFACE
inhibit
VITERBI DECODER
ERROR FLAG DETECT/COUNT
FIC
BUFFER SERIAL OUTPUT 49 to 50 47 46 to 44
55
51
52
54 53
43 56 58 57 59 RDC RDO
CFIC RESET
CCLK
SOC SOV[1:3] SFCO SOD[1:3] REF
CMODE CDATA
RDE
Fig.1 Block diagram.
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Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
7 PINNING SYMBOL ADC AIF VSSA ADE VDDA INP[0:9] ADCLK IQS BYP FSI FSO SLI AGC OSCI OSCO MCLK VSS PIN 1 2 3 99 100 8 to 17 19 20 21 22 23 24 25 4 5 41 7, 18, 26, 40, 60, 80 and 94 6, 28, 42 and 79 92 27 29 30 31 51 52 53 54 55 TYPE input input input input output input input input output output output input output output analog-to-digital converter IF input analog-to-digital converter enable (active LOW) 2048 kHz IF or baseband digital parallel input data (8 or 10 bits) DESCRIPTION analog-to-digital converter DC input
SAA3500H
ground analog supply ground supply analog voltage supply (+3.3 V) analog-to-digital clock output 8192 kHz if BYP = HIGH, 4096 kHz if BYP = LOW clock signal indicating I or Q baseband data if BYP = LOW; signal for swapping I and Q data bytes if BYP = HIGH IF input stage bypass (active LOW) frame sync input (LOW indicates DAB null symbol detection) null detector/frame sync output (LOW indicates DAB null symbol position) AGC synchronization lock indicator (HIGH if synchronized) AGC level comparator output (HIGH if input sample > reference level, else LOW) oscillator or system clock input, 24576 kHz oscillator output master clock output, 24576 kHz
supply digital supply ground
VDD
supply digital voltage supply (+3.3 V)
TEST OUT[0:7] OCLK OIQ OCIR OEN CFIC CMODE CDATA CCLK RESET A[17:11] A[10:0] WR RD A17 D[0:7] 2000 Jun 14
input output output input input output input I/O input input
connect to ground for proper operation baseband or channel impulse response output output data clock (negative edge indicates new data) output I or Q select signal if OCIR = HIGH, or frame trigger if OCIR = LOW output select: baseband if OCIR = HIGH, CIR if OCIR = LOW output enable (active LOW) microcontroller interface signal indicating Fast Information Channel (FIC) processing microcontroller interface mode input (only L3-bus) microcontroller interface serial data I2C-bus or L3-bus (5 V tolerant) microcontroller interface clock input I2C-bus or L3-bus chip reset input (active LOW) address outputs external RAM address outputs external RAM write data to RAM (active LOW) read data from RAM (active LOW) address bit 17 inverted for second RAM (128k x 8) data input/output external RAM 5
32 to 39 output
62 to 68 output 81 to 91 output 61 69 70 output output output
71 to 78 I/O
Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
SAA3500H
SYMBOL SOV3 SOV2 SOV1 SOD3 SOD2 SOD1 SOC REF SFCO RDC RDE RDO TDO TCK TDI TMS TRST
PIN 44 45 46 47 48 49 50 43 56 57 58 59 93 95 96 97 98
TYPE output output output output output output output output output output input output output input input input input serial output valid data 3 serial output valid data 2 serial output valid data 1 serial output data 3 serial output data 2
DESCRIPTION
serial output data 1 (from channel decoder) serial output clock (384 kHz continuous) receiver error flag [from Viterbi decoder, for Simple Full Capacity Output (SFCO)] simple full capacity output (direct from Viterbi decoder) receiver data clock (6144 kHz continuous) or SFCO clock (burst) RDI output enable (active LOW) receiver data interface bi-phase output boundary scan test serial output boundary scan test clock input boundary scan test serial input boundary scan test mode select input boundary scan test reset input
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Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
SAA3500H
100 VDDA 99 ADE
98 TRST
92 TEST
97 TMS
94 VSS 93 TDO
95 TCK
ADC AIF VSSA OSCI OSCO VDD VSS INP0 INP1
1 2 3 4 5 6 7 8 9
81 A10 80 VSS 79 VDD 78 D0 77 D1 76 D2 75 D3 74 D4 73 D5 72 D6 71 D7 70 A17 69 RD 68 A11 67 A12 66 A13 65 A14 64 A15 63 A16 62 A17 61 WR 60 VSS 59 RDO 58 RDE 57 RDC 56 SFCO 55 RESET 54 CCLK 53 CDATA 52 CMODE 51 CFIC SOC 50
MXXxxx
96 TDI
91 A0
90 A1
89 A2
88 A3
87 A4
86 A5
85 A6
84 A7
83 A8 SOD2 48
INP2 10 INP3 11 INP4 12 INP5 13 INP6 14 INP7 15 INP8 16 INP9 17 VSS 18 ADCLK 19 IQS 20 BYP 21 FSI 22 FSO 23 SLI 24 AGC 25 VSS 26 OCLK 27 VDD 28 OIQ 29 OCIR 30 OEN 31 OUT0 32 OUT1 33 OUT2 34 OUT3 35 OUT4 36 OUT5 37 OUT6 38 OUT7 39 VSS 40 MCLK 41 VDD 42 REF 43 SOV3 44 SOV2 45 SOV1 46 SOD3 47 SOD1 49
SAA3500H
Fig.2 Pin configuration.
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82 A9
Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
8 FUNCTIONAL DESCRIPTION
SAA3500H
The 2.048 MHz IF signal is digitized by an 8-bit flash Analog-to-Digital Converter (ADC), which samples at 8.192 MHz. The required input level is limited to a peak-to-peak voltage of 2 V. Due to a fast sample-and-hold circuit sub-sampling is possible, so that all IF frequencies of N x 8.192 2.048 MHz can be used. If a higher resolution ADC is wanted, an external ADC can be connected. The digital mixer accepts a 2.048 MHz IF signal at its input and converts it to baseband with In-phase (I) and Quadrature-phase (Q) components. The mixer frequency is adjusted on a DAB frame basis with 1 Hz resolution to prevent performance degradation. The mixer output signals are digitally filtered and subjected to internal Automatic Gain Control (AGC) before entering the subsequent Fast Fourier Transform (FFT) stage. The output of the digital AGC detectors indicates for each input sample whether the level is below or above the reference input level. By means of external filtering and gain control, the signal can be used to adjust the input signal level of the analog-to-digital converter (external AGC). The on-chip null detector operates on the digital baseband signal and indicates the coarse position of the DAB null symbol (FSO = LOW), which is used for time base initialization. The spacing of detected null symbols is used to detect the DAB transmission mode. The time base counts samples on a symbol and a frame basis in order to generate the internal control windows for the FFT and to generate a frame sync signal (FSO) during the null symbol. Initialization of the time base is determined by the null detector signal (FSI) and the selected DAB mode. After time base initialization the SAA3500H will be in symbol processing mode and the null detector will be deactivated. The OFDM symbol demodulator applies a real-time FFT and differential demodulation to the baseband signal. The output is quantized to 4-bit metrics for the Viterbi decoder. The position of the FFT window is adjusted on a DAB frame basis in order to avoid Inter-Symbol Interference (ISI).
The FFT result of the reference symbol is processed by the synchronization core, which performs two functions: estimation of the frequency error of the baseband signal, which is needed to adjust the digital mixer (AFC), and calculation of the Channel Impulse Response (CIR) to be used for positioning of the FFT window and the system clock. All timing and frequency control loops are realized in the synchronization core and can be influenced from the control interface. The Viterbi decoder is preceded by frequency and time de-interleaving of the incoming metrics in external RAM, to distribute burst errors caused by channel fading. Variable rate decoding is done with 3.072 Mb/s decision speed. Output bits are re-encoded and compared to corresponding input bits in order to generate an error flag signal. Sub-channel selection is done on a Capacity Unit (CU) basis. All standardized Unequal Error Protection (UEP) puncturing schemes for audio and Equal Error Protection (EEP) schemes for data are provided. Up to 64 sub-channels can be selected separately, which means virtually unlimited DAB decoding capabilities. The output interface provides a full-speed standardized Receiver Data Interface (RDI) for all sub-channel data. This allows to extend every DAB receiver with external decoders for all kind of services. A dedicated interface is provided for the Philips SAA2502H audio source decoder, which completes the DAB receiver. The system clock of 24.576 MHz, can be generated by an integrated DCXO, which is internally locked to the DAB signal. The clock is available on the MCLK pin to provide a synchronous clock to the MPEG decoder and microcontroller. The I2C-bus or L3-bus configurable control interface provides access to Automatic Frequency Control (AFC), Channel Impulse Response (CIR), Fast Information Channel (FIC) and sub-channel selection controls.
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Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
9 9.1 INTERFACE DESCRIPTION Input interface
SAA3500H
The input interface can be used in 3 different modes, depending on the bypass (BYP) and IQ Select (IQS) pins. Digital input data should be in two's complement format (optionally: offset binary) and synchronized with the ADCLK output signal. Input data are read on the rising edge of ADCLK. Table 1 BYP 0 1 1 Input modes IQS clk 0 1 DESCRIPTION digital baseband input sampled at 2048 kHz and with I and Q data multiplexed digital IF input sampled at 8192 kHz, internal I/Q demodulator digital IF input sampled at 8192 kHz, internal I/Q demodulator with I and Q swapped
In case of baseband input the IQ select signal shall indicate whether the current sample is either I or Q data (INP[9:0]).
ADCLK INP[9:0] IQS Q0 I1 Q1 I2 Q2
4096 kHz 10 bits 2048 kHz
Fig.3 Baseband input signals (BYP = LOW).
Digital IF input is, typically, at a frequency of 2048 kHz. It is possible to apply sub-sampling on a N x 8.192 2.048 MHz (N = 1, 2, 3,...,19) IF signal, but care should be taken with the jitter of the crystal clock, which is proportional to N.
ADCLK INP[9:0]
8192 kHz 10 bits
Fig.4 IF input signals [BYP = HIGH, IQS = LOW (no swap) or HIGH (swap)].
To use the on-chip null detector, pins FSI and FSO shall simply be connected to each other. When using an external null detector, the FSI input shall indicate the position of the null symbol in the baseband signal (FSI = LOW). The negative edge may have a maximum delay of 512 samples with respect to an ideal null detector. The delay compensation can be set via the I2C/L3 interface (register ATCWinControl). The FSI input provides edge jitter suppression of up to 40 samples starting from the first negative edge. Once the SAA3500H is in symbol processing mode, the FSI signal is ignored. During the null detection state, the Sync Lock Indicator (SLI) will be continuously LOW. 9.2 Memory interface
An external SRAM memory of either 128 or 256 kbytes is required to store the metrics from the data de-interleaver for half (432 CUs) or full (864 CUs) decoding capacity, respectively. The upper address line A17 is available both true and inverted (A17) to allow memory extension without an address decoder. 3.3 V RAMs should be used with either an 8 or (2 x) 4-bit data bus and an access time of 80 ns. Input data are read on the rising edge of RD, output data shall be latched on the rising edge of WR. 2000 Jun 14 9
Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
SAA3500H
A[17:0] D[7:0] RD WR
Fig.5 RAM access.
9.3
Parallel output interface
The digital parallel output interface can be used in 3 different modes depending on the OCIR and OEN select pins. Output data shall be latched on the falling edge of OCLK. Table 2 Parallel output modes X = don't care. OCIR OEN 0 1 X 0 0 1 DESCRIPTION channel impulse response sampled at 64 kHz, OIQ = frame trigger baseband sampled at 2048 kHz and with I and Q data multiplexed OUT[7:0], OIQ and OCLK disabled
By means of an external digital-to-analog converter, either the CIR or I/Q data can be displayed on an oscilloscope. Digital output data is clocked out on the falling edge of the OCLK output signal. In case of baseband output the OIQ signal indicates, if the current sample is either I or Q data.
OCLK OUT[7:0] OIQ Q I Q I Q
4096 kHz signed 2048 kHz
Fig.6 Baseband output signals (OCIR = HIGH, OEN = LOW).
OCLK OUT[7:0] OIQ
64 kHz unsigned trigger
Fig.7 CIR output signals (OCIR = LOW, OEN = LOW).
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Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
SAA3500H
In the CIR output mode the channel impulse response is clocked out in a burst of N (unsigned) samples at 64 kHz each frame after CIR processing (bit SyncBusy = logic 0). The edges of the frame trigger signal (OIQ) allow to trigger a CIR display either at the start of the symbol or at the start of the symbol guard. In the latter case the CIR peak for a Gaussian channel will be at the left of the display. 9.4 Serial output interface
The serial output interface is intended for transferring up to three sub-channels to the source decoder(s) with a total maximum bit rate of 384 kbit/s. The sub-channels for these outputs should be selected with the appropriate I2C or L3 commands. The output clock is 384 kHz. Each sub-channel has its own serial data and data valid line, but the clock is common. Serial output data shall be latched on the rising edge of SOC.
SOC SOD SOV
Fig.8 DAB3 serial output.
9.5
Simple full capacity output
This interface provides serial access to all the Viterbi decoder output bits without any formatting. Transmission framing is indicated by the CFIC window, which can also be used to separate the FIC data (CFIC = HIGH) from the Main Service Channel (MSC) data (CFIC = LOW). The bit CFICMode can be used to signal on CFIC the beginning of the selected sub-channels (CFICMode = logic 0). The clock is a 3072 kHz burst clock, activated for each new output bit. Accompanied with the data is the error flag, obtained by re-encoding the Viterbi output bits and comparison with the corresponding Viterbi decoder input bits (REF = HIGH for error bit).
CFIC RDC SFCO REF
CFICMode = 0
Fig.9 Simple full capacity output (CFICMode = logic 1).
9.6
RDI output
For external use a bi-phase modulated output (RDO) is provided, which carries all the FIC and MSC data, formatted according to the DAB receiver data interface specification "EN 50255", which is based on the IEC 60958 digital audio interface. Optionally, a clock (6144 kHz) and word select signal (48 kHz) can be provided (instead of SFCO signals). Transmitter Identification Information (TII) is not signalled on this RDI. The FIC however is always signalled, with the Cyclic Redundancy Check (CRC) performed and the Error Check Field containing the resulting CRC (normally 0). Selected sub-channels will be directed to the RDI interface in the extended capacity mode (22 bits for MSC), but the number of RDI frames and the reliability are not signalled (i.e., set to all logic 0s and all logic 1s, respectively). 2000 Jun 14 11
Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
SAA3500H
RDO
Fig.10 RDI output (normal mode, RDE = LOW).
In case SFCO data output is not desired, a particular `RDI plus' mode can be selected, which provides a continuous 6144 kHz clock on RDC, synchronous to the bi-phase RDI data and accompanied by a fixed word select signal, to allow RDI source reception without an extra clock recovery circuit. Output data shall be latched on the rising edge of RDC.
RDC RDO SFCO Channel 1 (32 bits) Channel 2 (32 bits)
Fig.11 RDI output (RDI plus mode, RDE = LOW).
9.7
Microcontroller interface
The microcontroller interface of the SAA3500H operates in one of two distinct modes of operation: I2C-bus or L3-bus. Mode setting is determined at initialization, as described in Fig.12. On either control bus data are transferred in 8-bit packets, or bytes. The interface uses three signals and the function in the L3-bus mode or I2C-bus mode is indicated in Table 3. Table 3 Control bus modes L3-BUS MODE L3DATA L3CLK L3MODE I2C-BUS MODE SDA SCL none DIRECTION input/output input input DESCRIPTION microcontroller interface serial data microcontroller interface bit clock microcontroller interface mode select
SIGNAL CDATA CCLK CMODE
During a hard reset of the device, the microcontroller interface mode is determined. As a consequence, the interface cannot be used while the reset signal is asserted. Mandatory action must be taken for correct microcontroller interface start-up at a hard reset, as explained in Fig.12.
RESET CMODE CCLK
phase 1 phase 2 phase 3
I2C-bus mode L3-bus mode
Fig.12 Microcontroller interface initialization procedure.
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Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
SAA3500H
In phase 1, the level of the CMODE signal determines the microcontroller interface mode, while reset is asserted. CMODE = HIGH defines I2C-bus mode, CMODE = LOW defines L3-bus mode. No transfers can be performed, as CCLK must be HIGH. In phase 2, which is for L3-bus mode of operation only, it is mandatory to take CMODE HIGH, then LOW again after reset has been de-asserted, to correctly initialize the interface unit. This must occur before any L3-bus transfer (even to or from other devices) is performed. CCLK shall remain HIGH during this phase. In phase 3, the first transfer can be performed on the microcontroller interface. Any deviation from these steps may result in undefined behaviour of the microcontroller interface, even with the possibility of disturbing transfers to other devices connected to the control bus. At a hardware reset, all writeable data items are forced to their default values. The microcontroller interface provides access to all blocks, which generate or need control information. Selections on the SAA3500H are at the sub-channel level, the required sub-channel parameters should be obtained via the Multiplex Configuration Information (MCI), which is part of the FIC. The CFIC window from the SAA3500H indicates FIC decoding. FIC data from the I2C/L3 interface will be invalid, if CFIC = HIGH. It is therefore recommended to connect CFIC to a microcontroller interrupt input pin. With regard to the real-time processing requirements, it is highly recommended to use a 16-bit microcontroller. 9.7.1 I2C-BUS MODE
The implemented I2C-bus interface is of the 400 kbit/s, 7-bit address type. The CDATA output driver is of the `open drain' type in order to be compliant with the I2C-bus specification. The device address is as follows: Table 4 I2C-bus device address BIT 6 1 BIT 5 0 BIT 4 1 BIT 3 0 BIT 2 1 BIT 1 1 BIT 0 R/W
BIT 7 1
Bit 7 to bit 1 comprise the 7-bit I2C-bus slave address, while bit 0 indicates the transfer direction of data and acknowledge bits as follows: Table 5 R/W 0 1 Read and write operation to the microcontroller in I2C-bus mode FUNCTION data from microcontroller to SAA3500H data from SAA3500H to microcontroller REMARK all acknowledge generated by SAA3500H acknowledge for data generated by microcontroller
Fundamentals of the I2C-bus interface protocol are shown in Fig.13.
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Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
SAA3500H
CCLK
1
2
7
8
9 ACK
1
2
7 data transfer
8
9 ACK
address transfer
CDATA
S START condition
MSB
R/W
MSB
LSB P STOP condition
Fig.13 I2C-bus data transfer example.
For full details of the I2C-bus interface specification, please, refer to the I2C-bus specification (http://www.semiconductors.com/handbook/various_38.html), which is also available on request. 9.7.2 L3-BUS MODE
The L3-bus device address is composed as follows: Table 6 L3-bus device address BIT 6 1 BIT 5 1 BIT 4 0 BIT 3 1 BIT 2 1 BIT 1 DOM1(1) BIT 0 DOM0(1)
BIT 7 0 Note
1. The `Data Operation Mode' bits DOM1 and DOM0 define the current sub-mode of the microcontroller interface until the next time a device address is received (see Table 7). Table 7 DOM1 0 0 1 1 Read and write operation to the microcontroller in L3-bus mode DOM0 0 1 0 1 FUNCTION data from microcontroller to SAA3500H data from SAA3500H to microcontroller control from microcontroller to SAA3500H status from SAA3500H to microcontroller REMARK general purpose data transfer general purpose data transfer register selection for data transfer short device status message
Fundamentals of the L3-bus interface protocol are shown in Fig.14.
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Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
SAA3500H
CCLK CMODE CDATA
1
2
7
8
1
2 data mode
7
8
addressing mode
LSB
MSB
LSB
MSB
Fig.14 L3-bus command transfer example.
For full details of the L3-bus interface specification, please, refer to the SAA2502H data sheet (order number 9397 750 03068 or at http://www.semiconductors.com/products). 9.7.3 MICROCONTROLLER INTERFACE REGISTERS
Communication between the microcontroller and the SAA3500H is by addressing registers and writing or reading data. All addresses and register contents are in hexadecimal notation. The following registers are available for the writing of data: Table 8 Writeable registers NAME Control Configuration CIFCount CurSubChSel NextSubChSel SOD1 SOD2 SOD3 AGCExternal AGCInternal AGCFixed NullDetMargin TIIControl MixerFreqInput CarrierShift AFCGain ATCWinControl CIRThreshold ATCGains control configuration CIF count and occurrence change flag current sub-channel selection next sub-channel selection select sub-channel for serial output SOD1 select sub-channel for serial output SOD2 select sub-channel for serial output SOD3 setting of thresholds for external AGC settings of the internal AGC internal AGC switch off and fixed gain setting null detector margin TII main/sub identifier digital mixer frequency control input carrier shift by n carrier positions AFC loop gain ATC window control input or FFT window position and null detector delay compensation CIR detector thresholds, edge and range ATC loops gains; clock I and P gains and window gain DESCRIPTION SETTING AFTER RESET (HEX) 1F FF 00 00 00 00 00 00 00 00 00 00 00 40 40 40 61 0C D0 49 00 40 00 00 80 00 00 00 10 96 02 02 02 04 20
ADDRESS (HEX) 00 01 10 20 21 30 31 32 40 41 42 50 51 60 62 63 70 71 73
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Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
The following registers are available for the reading of data: Table 9 Readable registers NAME Status FICErrCount FICData TIIOutput CarrierDev ATCWinOutput ATCDetector CIRPower DESCRIPTION internal processing status FIC error count per frame FIC data inclusive CRC result TII complex phase values AFC carrier deviation detector ATC window loop output for FFT window position ATC CIR detector output power of CIR response
SAA3500H
ADDRESS (HEX) 00 10 20 to 2B 51 60 61 70 71 72 76
BYTES TO READ 1 2 32 6 3 2 1 3 1 2
AFCLoopOutput AFC loop output for digital mixer frequency control
ATCClockOutput ATC clock loop output for external VCXO
A description of how to use the individual registers is given in a separate application note. 10 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VDD Vi IDD Ii Io Ptot Tstg Tamb Ves input voltage supply current input current output current total power dissipation storage temperature operating ambient temperature electrostatic handling voltage note 2 note 3 Notes 1. All supply connections must be made to the same external power supply unit. 2. Machine model: equivalent to discharging a 200 pF capacitor through a 0 series resistor (`0 ' is actually 0.75 H + 10 ). 3. Human body model: equivalent to discharging a 100 pF capacitor through a 1500 series resistor. 11 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER CONDITIONS VALUE 60 UNIT K/W PARAMETER DC supply voltage CONDITIONS note 1 MIN. -0.5 -0.5 - -10 -10 - -65 -40 -300 -3000 MAX. +6 VDD + 0.5 200 +10 +10 650 +150 +85 +300 +3000 V V mA mA mA mW C C V V UNIT
thermal resistance from junction to ambient in free air
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Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
SAA3500H
12 DC CHARACTERISTICS VDD = 3.0 to 3.6 V; Tamb = -40 to +85 C; all voltages referenced to ground (VSS); unless otherwise specified. SYMBOL Supplies VDD(tot) IDD(tot) Dissipation Ptot Inputs CMOS LEVEL INPUT (INP[9:0], FSI, CCLK AND TCK) VIH VIL |ILI| Ci VIH VIL Rpu(VDD)(int) Ci VIH(hys) VIL(hys) Vhys Rpu(VDD)(int) Ci HIGH-level input voltage LOW-level input voltage input leakage current input capacitance 2.0 - VI = 0 or VI = VDD - - 2.0 - 16 - 1.4 0.9 0.4 16 - - - - 5 - - 33 5 - - - 33 5 - 0.8 1 - - 0.8 78 - 1.9 1.45 0.7 78 - V V A pF total power dissipation - - 650 mW total DC supply voltage total DC supply current note 1 3.0 - 3.3 - 3.6 180 V mA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
CMOS LEVEL INPUT, PULL-UP (BYP, CMODE, IQS, OCIR, OEN, RDE, TDI, TMS AND TRST) HIGH-level input voltage LOW-level input voltage internal pull-up resistor to VDD input capacitance V V k pF
CMOS LEVEL INPUT, HYSTERESIS, PULL-UP (RESET) HIGH-level hysteresis input, rising edge LOW-level hysteresis input, falling edge hysteresis voltage internal pull-up resistor to VDD input capacitance V V V k pF
Inputs/outputs CMOS LEVEL INPUT, HYSTERESIS, OPEN DRAIN OUTPUT (CDATA) VIH(hys) VIL(hys) Vhys VOL VIH VIL |ILI| VOH VOL HIGH-level hysteresis input, rising edge LOW-level hysteresis input, falling edge hysteresis voltage LOW-level output voltage
OUTPUT STAGE
1.4 0.9 0.4 ILOAD = 3 mA - 2.0 - VI = 0 or VI = VDD - ILOAD = -1.5 mA ILOAD = 1.5 mA 2.4 -
- - - - - - - - -
1.9 1.45 0.7 0.4 - 0.8 1 - 0.4
V V V V
CMOS LEVEL INPUT, 1.5 mA
(D[7:0]) V V A V V
HIGH-level input voltage LOW-level input voltage input leakage current HIGH-level output voltage LOW-level output voltage
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Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
SAA3500H
SYMBOL Outputs CMOS LEVEL, 1.5 mA AND WR) VOH VOL CLOAD VOH VOL |ILO|
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
OUTPUT STAGE
(A[17:0], A17, ADCLK, AGC, FSO, OCLK, OIQ, RD, SLI, SOD[1:3], SOV[1:3] ILOAD = -1.5 mA ILOAD = 1.5 mA 2.4 - - ILOAD = -1.5 mA ILOAD = 1.5 mA inactive mode; VO = 0 or VO = VDD 2.4 - - - - - - - - - 0.4 30 - 0.4 1 V V pF
HIGH-level output voltage LOW-level output voltage output load capacitance
CMOS LEVEL, 1.5 mA 3-STATE OUTPUT STAGE, (OUT[7:0]) HIGH-level output voltage LOW-level output voltage output leakage current V V A
CLOAD VOH VOL CLOAD Note
output load capacitance
OUTPUT STAGE
- ILOAD = -3 mA ILOAD = 3 mA 2.4 - -
- - - -
30 - 0.4 50
pF
CMOS LEVEL, 3 mA
(CFIC, MCLK, RDC, RDO, REF, SFCO, SOC AND TDO) V V pF
HIGH-level output voltage LOW-level output voltage output load capacitance
1. All supply connections must be made to the same external power supply unit. 13 AC CHARACTERISTICS VDD = 3.0 to 3.6 V; Tamb = 25 C; all voltages referenced to ground (VSS); unless otherwise specified. SYMBOL Oscillator input (OSC) fi(OSC) OSC tCL,RESET input frequency input clock duty factor note 1 - 40 60 x T 24576 - - - 60 - kHz % PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Reset input (RESET) reset LOW duration note 2 ns
Input interface (ADCLK, BYP, INP[9:0] and IQS) BASEBAND INPUT (BYP = LOW); see Fig.15 Tcy,ADCLK tCL,ADCLK tCH,ADCLK th,INP th,IQS ADCLK cycle time ADCLK LOW time ADCLK HIGH time INP[9:0] hold time IQS hold time - - - 5 - 244 122 122 - - - - - - 80 ns ns ns ns ns
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Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
SAA3500H
SYMBOL
PARAMETER
CONDITIONS - - - 5 - - - - - - 0 - -
MIN.
TYP. - - - -
MAX.
UNIT
IF INPUT (BYP = HIGH); see Fig.16 Tcy,ADCLK tCL,ADCLK tCH,ADCLK th,INP td,INP Tcy,A tCL,RD td,RD th,RD tCL,WR td,WR td,D th,D ADCLK cycle time ADCLK LOW time ADCLK HIGH time INP[9:0] hold time INP[9:0] delay time 122 80 42 - - 326 163 40 0 163 40 0 - ns ns ns ns ns
25 - - - - - - - 5
Memory interface (A17, A[17:0], D[7:0], RD and WR); see Figs 17 and 18 address cycle time RD LOW time RD delay time RD hold time WR LOW time WR delay time data delay time data hold time ns ns ns ns ns ns ns ns
Parallel output interface (OCIR, OCLK, OEN, OIQ and OUT[9:0]) BASEBAND OUTPUT (OCIR = HIGH); see Fig.19 Tcy,OCLK tCL,OCLK tCH,OCLK tsu,OUT tsu,OIQ Tcy,OCLK tCL,OCLK tCH,OCLK tsu,OUT tsu,OIQ Tcy,SOC tCL,SOC tCH,SOC th,SOD tsu,SOV th,SOV OCLK cycle time OCLK LOW time OCLK HIGH time OUT[7:0] set-up time OIQ set-up time - - - - - - - - - - - - - - - - 244 122 122 15 17 - - - - - - - - - - - - - - - - ns ns ns ns ns s s s ns ns s s s ns ns ns
CIR OUTPUT (OCIR = LOW); see Fig.20 OCLK cycle time OCLK LOW time OCLK HIGH time OUT[7:0] set-up time OIQ set-up time 15.6 8.3 7.3 0 0
Serial output interface (SOC, SOD[3:1] and SOV[3:1]); see Fig.21 SOC cycle time SOC LOW time SOC HIGH time SOD hold time SOV set-up time SOV hold time 2.6 1.3 1.3 0 4 2
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Preliminary specification
Digital audio broadcast channel decoder
SAA3500H
SYMBOL
PARAMETER
CONDITIONS - - - -
MIN.
TYP. - - - - - - - - - - - - - -
MAX.
UNIT
Simple full capacity output interface (CFIC, RDC, REF and SFCO); see Fig.22 tCH,CFIC CFIC HIGH time DAB mode I DAB mode II DAB mode III DAB mode IV tSH,CFIC tsu,CFIC th,CFIC Tcy,RDC tCH,RDC tCL,RDC tsu,SFCO tsu,REF th,REF CFIC strobe HIGH time CFIC set-up time CFIC hold time RDC cycle time RDC HIGH time RDC LOW time SFCO set-up time REF set-up time REF hold time 3.738 0.935 1.246 1.869 75 0 165 80 - - 75 5 165 -160 ms ms ms ms ns ns ns ns ns ns ns ns ns ns
bit CFICMode = 0 - bit CFICMode = 1 - - - 325 250 - - - -
RDI output interface (RDC, RDE, RDO and SFCO) NORMAL MODE; see Fig.23 tONE tZERO Tcy,RDC tCH,RDC tCL,RDC Tcy,SFCO tCH,SFCO tCL,SFCO tsu,SFCO th,SFCO ONE time ZERO time - - - - - - - - - - 163 326 - - - - - - - - - - ns ns
RDI PLUS MODE; see Fig.24 RDC cycle time RDC HIGH time RDC LOW time SFCO cycle time SFCO HIGH time SFCO LOW time SFCO set-up time SFCO hold time 163 86 77 20.8 10.4 10.4 4 0 ns ns ns s s s ns ns
Microcontroller interface INITIALIZATION PROCEDURE; see Fig.25 tCL,RESET td,RES-MOD tCH,CMODE td,MOD-CLK RESET LOW time delay time from RESET to CMODE CMODE HIGH time delay time from CMODE to first CCLK note 2 note 2 note 2 note 2 60 x T 10 x T 10 x T 10 x T - - - - - - - - ns ns ns ns
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Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
SAA3500H
SYMBOL
PARAMETER
CONDITIONS
MIN. - - - - - - - - - - - - - -
TYP. - - - - - - -
MAX.
UNIT
L3-BUS MICROCONTROLLER TO SLAVE DEVICE; see Figs 26 and 28 tcL tcH td1 th1 th2 tsu tL td2 td3 td4 td5 th3 tf,I2C fCCLK Notes 1. In a real application, the clock frequency may vary in a range of 50 ppm due to timing synchronization. 2. T = 4 x OSC cycle time, i.e., T = 163 ns at fosc = 24.576 MHz. L3CLK LOW time L3CLK HIGH time L3MODE set-up time before first L3CLK LOW L3DATA hold time after L3CLK HIGH L3MODE hold time after last L3CLK HIGH L3DATA set-up time before L3CLK HIGH L3MODE LOW time note 2 note 2 note 2 note 2 T + 10 T + 10 10 10 15 T + 10 T + 10 ns ns ns ns ns ns ns
L3-BUS SLAVE DEVICE TO MICROCONTROLLER; see Fig.27 L3MODE HIGH to L3DATA enabled time L3MODE HIGH to L3DATA stable time L3CLK HIGH to L3DATA stable time L3MODE LOW to L3DATA disabled time L3DATA hold time after L3CLK HIGH (CDATA AND CCLK) - - 250 400 ns kHz note 2 note 2 0 - - 0 T 20 20 2T + 30 20 - ns ns ns ns ns
I2C-BUS INPUTS/OUTPUT
output fall time CCLK clock frequency
Tcy,ADCLK tCL,ADCLK ADCLK INP[9:0] th,INP IQS th,IQS tCH,ADCLK
Fig.15 Baseband input timing (BYP = LOW).
Tcy,ADCLK tCL,ADCLK ADCLK INP[9:0] th,INP
tCH,ADCLK
td,INP
Fig.16 IF input timing [BYP = HIGH, IQS = LOW (no swap) or HIGH (swap)].
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Preliminary specification
Digital audio broadcast channel decoder
SAA3500H
Tcy,A
A[17:0] D[7:0] tCL,RD RD td,RD th,D WR A[17:0] D[7:0] td,D td,WR
Tcy,A
th,D tCL,WR
Fig.17 RAM access read timing.
Fig.18 RAM access write timing.
Tcy,OCLK tCL,OCLK OCLK OUT[7:0] tsu,OUT OIQ tsu,OIQ OIQ tCH,OCLK OCLK OUT[7:0] tsu,OIQ
Tcy,OCLK tCL,OCLK tCH,OCLK
tsu,OUT
Fig.19 Baseband output timing (OCIR = HIGH, OEN = LOW).
Fig.20 CIR output timing (OCIR = LOW, OEN = LOW).
Tcy,SOC tCL,SOC SOC th,SOD SOD SOV tsu,SOV th,SOV tCH,SOC
Fig.21 DAB3 serial output timing.
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Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
SAA3500H
tCH,CFIC tsu,CFIC CFIC th,CFIC tSH,CFIC
Tcy,RDC tCH,RDC tCL,RDC
RDC SFCO tsu,SFCO REF tsu,REF th,REF
Fig.22 Simple full capacity output timing.
tONE tZERO RDO
Fig.23 RDI output timing (normal mode, RDE = LOW).
Tcy,RDC RDC RDO
tCL,RDC
tCH,RDC
th,SFCO tCL,SFCO SFCO
tsu,SFCO
tCH,SFCO Tcy,SFCO
Fig.24 RDI output timing (RDI plus mode, RDE = LOW).
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Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
SAA3500H
tCL,RESET RESET CMODE CCLK
tCH,CMODE
td,RES-MOD
td,MOD-CLK
Fig.25 Microcontroller interface initialization timing.
handbook, full pagewidth
t d1 L3MODE t cL t cH
t h2
L3CLK
L3DATA t su t h1
MGB507
Fig.26 Timing of L3-bus addressing mode.
handbook, full pagewidth
t d1 L3MODE t cL L3CLK t su t h1 t cH
t h2
L3DATA microcontroller to IC L3DATA IC to microcontroller t d2 t d3
t h3
t d4
t d5
MGB508
Fig.27 Timing of L3-bus data transfer mode.
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Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
SAA3500H
handbook, full pagewidth
tL L3MODE t h2 L3CLK td5 L3DATA IC to microcontroller
MGB509
t d1
t d2
Fig.28 Timing of L3-bus halt mode.
14 APPLICATION INFORMATION A suggestion for an application block diagram is shown in Fig.29.
RAM (256k x 8)
A D
RDI SAA2502H I2S L/R SPDIF
TUNER BAND III/L
SAW FILTER AGC
SAA3500H
DAB3
24.576 MHz MICROCONTROLLER I2C or L3-BUS
Fig.29 Typical application diagram.
14.1
Clock oscillator
14.2
Reset input
To perform automatic fine tuning of the clock signal, the microcontroller reads data from the SAA3500H and controls an external (VCXO) crystal oscillator. The following requirements should be met by that oscillator: Table 10 VCXO specification PARAMETER Frequency Pull range Operating temperature Frequency drift with temperature Tolerance and ageing VALUE 24576 50 -40 to +85 20 10 UNIT kHz ppm C ppm ppm
The reset signal is active LOW and should have a minimum duration of 60 clock cycles. 14.3 Boundary scan test interface
For normal operation set TRST LOW, TCK LOW or HIGH, TDI and TMS not connected or HIGH. The boundary scan chain has a length of 84 and a 5-bit instruction code.
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Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
15 PACKAGE OUTLINE QFP100: plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.7 mm; high stand-off height
SAA3500H
SOT317-1
c
y X
80 81
51 50 ZE
A
e E HE A A2 A1 (A 3) Lp bp 100 1 wM D HD ZD B vM B 30 vM A 31 detail X L
wM pin 1 index
e
bp
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 3.3 A1 0.36 0.10 A2 2.87 2.57 A3 0.25 bp 0.40 0.25 c 0.25 0.13 D (1) 20.1 19.9 E (1) 14.1 13.9 e 0.65 HD 24.2 23.6 HE 18.2 17.6 L 1.95 Lp 1.0 0.6 v 0.2 w 0.15 y 0.1 Z D (1) Z E (1) 0.8 0.4 1.0 0.6 7 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT317-1 REFERENCES IEC JEDEC MO-112 EIAJ EUROPEAN PROJECTION
ISSUE DATE 97-08-01 99-12-27
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Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
16 SOLDERING 16.1 Introduction to soldering surface mount packages
SAA3500H
* Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 16.4 Manual soldering
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. 16.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. 16.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
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Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
16.5 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, SQFP PLCC(3), SO, SOJ not suitable suitable(2) suitable not recommended(3)(4) not recommended(5) suitable suitable suitable suitable suitable HLQFP, HSQFP, HSOP, HTSSOP, SMS not LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes
SAA3500H
REFLOW(1)
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
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Preliminary specification
Digital audio broadcast channel decoder
17 DATA SHEET STATUS DATA SHEET STATUS Objective specification PRODUCT STATUS Development DEFINITIONS (1)
SAA3500H
This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Preliminary specification
Qualification
Product specification
Production
Note 1. Please consult the most recently issued data sheet before initiating or completing a design. 18 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 20 PURCHASE OF PHILIPS I2C COMPONENTS 19 DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
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Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
NOTES
SAA3500H
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Philips Semiconductors
Preliminary specification
Digital audio broadcast channel decoder
NOTES
SAA3500H
2000 Jun 14
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Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 2000
Internet: http://www.semiconductors.philips.com
SCA 69
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753503/01/pp32
Date of release: 2000
Jun 14
Document order number:
9397 750 07187

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